The present invention relates to electronic devices that have power saving modes of operation and, more particularly, to waking up a processor from a deep sleep mode.
There is a great demand for high (gigahertz) performance from embedded processors that include so called “green” technology or power management and energy saving features. For example, printers and other office automation equipment (i.e., peripheral devices) that have cyclical workloads usually include a sleep or hibernate mode in which the device is powered down when not used for a predetermined time period. The device is awakened when a power or other button is pressed. While such a scheme provides great power savings, this scheme needs to be modified when applied to processors or systems that are connected to a network because network transmissions must be constantly analyzed by the device to determine whether or not it must act on such transmissions. Further, processors cannot afford the time it takes to wake up from a full power down state or they may lose data that is being transmitted to them. Thus, processors now allow for varying levels of power down, which may be called sleep mode, deep sleep mode, and the like.
Processors connected to a network include a network interface circuit or network interface card. When in a sleep mode, the processor and other modules may be powered down but the network interface circuit remains active so that data packets can be received and analyzed. If an interesting packet is received, then the network interface circuit sends a signal or interrupt to the processor to awaken it, otherwise the packet is discarded.
An improvement to this scheme is to connect a memory or buffer to the network interface circuit and buffer the packets that arrive after receipt of an interesting packet so that data is not lost while the processor is transitioning from the sleep mode. However, data may be lost if the size of the buffer is not adequate or the processor cannot transition quickly from the sleep mode. Thus, a further improvement is to slow down the speed of the network when the processor is sleeping or waking up, which decreases the number of packets that will be received and must be stored in the buffer.
The above described approaches still fall short of optimal power reduction because they either require a large buffer so as not to lose data (a larger buffer consumes more power) and because the processor usually does not remain in the sleep mode very long before it is interrupted due to receipt of an interesting data packet. That is, the average standby time is low because the device frequently wakes up. Accordingly, it would be advantageous to have a processor that provides for additional energy savings.